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1 rev 1.1 CW24C02/ cw24c04/ cw24c08/ cw24c16 description features 2kbit, 4kbit, 8kbit and 16kbit serial i2c bus eeprom pin configuration september. 2007 applications intelligent instrument industrial controller household appliance automotive electronics the CW24C02/04/08/16 is electrically erasable prom. the device is organized as one block of 256/512/1024/2048 x 8-bit memory with 2-wire serial interface. low-voltage design permits operation down to 1.8v, with standby and active currents of only 1a and 1ma respectively. the CW24C02/04/08/16 also has a page write capability for up to 8/16/16/16 bytes of data. wide voltage operation v cc = 1.8v to 5.5v internally organized: - CW24C02, 256 x 8 (2k bits) - cw24c04, 512 x 8 (4k bits) two-wire serial interface, fully i2c bus compatible 1 mhz (5v), 400 khz (1.8v, 2.5v, 2.7v) compatibility schmitt trigger inputs for noise suppression write protect pin for hardware data protection self-timed write cycle (5 ms max) high-reliability - endurance: 1 million write cycles - data retention: 100 years dip8l, sop8l,tss op8 and dfn8 packages low-power technology - 1ma active current typical - 1a standby current typical byte and multi-byte write page write, 8-byte page (CW24C02), 16-byte page (cw24c04/08/16) byte, random and sequential read mode automatic address incrementing esd protection > 2.5kv pb-free finish available, rohs compliant computer/notebook communication - cw24c08, 1024 x 8 (8k bits) - cw24c16, 2048 x 8 (16k bits) sda scl wp v cc 1 2 3 4 8 7 6 5 nc a1 a2 gnd sda scl wp v cc 1 2 3 4 8 7 6 5 nc nc nc gnd sda scl wp v cc 1 2 3 4 8 7 6 5 nc nc a2 gnd (top view) sda scl wp v cc 1 2 3 4 8 7 6 5 a0 a1 a2 gnd c02 c04 c08 c16 free datasheet http:///
2 rev 1.1 CW24C02/ cw24c04/ cw24c08/ cw24c16 2kbit, 4kbit, 8kbit and 16kbit serial i2c bus eeprom september. 2007 ordering information temperature range package orderable device package qty. -40c to +85c sop8l dip8l pb-free cw24cxxp cw24cxxd cw24cxxdr cw24cxxt 50 units/tube 100 units/tube 3000 units/r&t 4000 units/r&t tssop8 xx=02/04/08/16 figure 1. block diagram block diagram nc / nc / nc / a0 nc / nc / a1 / a1 nc / a2 / a2 / a2 c16 / c08 / c04 / c02 sda scl wp v cc gnd start stop logic serial control logic device address comparator data word address counter load comp load inc y decoder high voltage pump/timing en data recovery eeprom serial mux r e d o c e d x dout/acknowledge din dout dfn8 cw24cxxf 3000 units/r&t
3 rev 1.1 CW24C02/ cw24c04/ cw24c08/ cw24c16 september. 2007 v absolute maximum ratings parameter symbol unit dc supply voltage dc output voltage storage temperature v cc dc input voltage v in v out t stg value -0.3 to v cc +0.3 -0.3 to v cc +0.3 -0.3 to +6.5 c -65 to +150 (maximum ratings are those values beyond which damage to the device may occur.) v v electrostatic discharge voltage (human body model) electrostatic discharge voltage (machine model) dc output voltage storage temperature v esd 2500 200 v v v c recommended operating conditions parameter symbol unit dc supply voltage v cc operating temperature t a max +85 5.5 min 1.8 -40 (functional operation should be restricted to the recommended operating conditions.)
4 rev 1.1 CW24C02/ cw24c04/ cw24c08/ cw24c16 september. 2007 ma dc electrical characteristics parameter symbol unit standby current supply current min i cc v cc =5v test conditions 1.0 read at 100khz 3.0 3.0 output low level a 3.0 1.0 -0.6 v 0.4 v in = v cc or gnd 0.05 (applicable over recommended operating range from: t a = -40c to +85c, v cc = +1.8v to +5.5v,unless otherwise noted) max input low level a v il typ ma 0.4 2.0 v cc =5.0v, i ol = 3.0 ma 0.2 0.4 write at 100khz v cc 0.7 v cc 0.3 i sb v in = v cc or gnd v out = v cc or gnd a input leakage current output leakage current i li i lo v ih input high level v cc +0.5 v v v v v ol3 v ol2 v ol1 v cc =3.0v, i ol = 2.1 ma v cc =1.8v, i ol = 0.15 ma ac electrical characteristics (applicable over recommended operating range from t a = -40c to +85c, v cc = +1.8v to +5.5v, c l = 100 pf,unless otherwise noted) parameter symbol unit clock pulse width high clock frequency, scl min f scl test conditions 400 v cc =1.8v 1000 ns 0.05 0.05 0.6 0.9 0.6 max s typ khz 1.2 0.55 40 v cc =5v 0.4 t low s noise suppression time clock low to data out valid t i t aa 50 t high clock pulse width low s v cc =1.8v v cc =5v v cc =1.8v v cc =5v v cc =1.8v v cc =5v v cc =1.8v v cc =5v capacitance (applicable over recommended operating range from t a = 25c, f = 1.0 mhz, v cc = +1.8v) pf parameter symbol unit input/output capacitance (sda) c i/o input capacitance (a0, a1, a2, scl) c in max 6 8 min pf test conditions v i/o = 0v v in = 0v 1.2 time the bus must be free before a new transmission can start t buf 0.5 s v cc =1.8v v cc =5v
5 rev 1.1 CW24C02/ cw24c04/ cw24c08/ cw24c16 september. 2007 ac electrical characteristics(continued) inputs rise time data in hold time 0 ns 50 0.6 5 0.25 ns t wr ns 100 ns stop setup time data out hold time t r t dh t f data in setup time s ms inputs fall time write cycle time t su.sto v cc =1.8v v cc =5v v cc =1.8v v cc =5v s 300 100 300 t hd.dat t su.dat figure 2. bus timing figure 3. write cycle timing scl sda_in sda_out t f t low t su.sta t hd.sta t aa t dh t buf t su.sto t r t hd.dat t su.dat t high t low 8th bit scl sda ack stop condition start condition t wr (1) t hd.sta s start hold time start setup time t su.sta v cc =1.8v v cc =5v v cc =1.8v v cc =5v s 0.6 0.25 0.6 0.25 parameter symbol unit min test conditions max typ note 1. the write cycle time t wr is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
6 rev 1.1 CW24C02/ cw24c04/ cw24c08/ cw24c16 september. 2007 pin description no. name 3 1 function description 5 6 2 4 7 a0 a1 a2 sda scl wp gnd v cc address input. the a2, a1 and a0 pins are device address inputs. the CW24C02 uses the a2, a1 and a0 inputs for hard wire addressing and a total of eight CW24C02 devices may be addressed on a single bus system (device addressing is discussed in detail under the device addressing section). the cw24c04 uses the a2 and a1 inputs for hard wire addressing and a total of four cw24c04 devices may be addressed on a single bus system. the a0 pin is a no connect and can be connected to gnd. the cw24c08 only uses the a2 input for hardwire addressing and a total of two cw24c08 devices may be addressed on a single bus system. the a0 and a1 pins are no connects and can be connected to gnd. the cw24c16 does not use the device address pins, which limits the number of devices on a single bus to one. the a0, a1 and a2 pins are no connects and can be connected to gnd. serial address and data i/o. the sda pin is bi-directional for serial data transfer. it is an open-drain device, therefore the sda bus requires a pull-up resistor to v cc (typical 10k). serial clock input. the scl input is used to synchronize the data transfer to and from each eeprom device. its positive edge clock data into the device and negative edge clock data out of the device. 8 write protect. the wp pin that provides hardware data protection. the wp pin allows normal read/write operations when connected to ground (gnd). when the wp pin is connected to v cc , the write protection feature is enabled and read only. circuit ground pin. positive supply voltage. memory organization device total bits total pages bytes per page word address CW24C02 cw24c04 cw24c08 cw24c16 2k 4k 8k 16k 32 32 64 128 8 16 16 16 8-bit 9-bit 10-bit 11-bit
7 rev 1.1 CW24C02/ cw24c04/ cw24c08/ cw24c16 september. 2007 detailed operating information i2c data bus and transmission protocol i2c-bus interface the cw24cxx supports i2c-bus transmission protocol. the i2c-bus is a bidirectional, two-line communication interface. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor. a typical bus configuration using this 2-wire protocol is show in figure 4. figure 4. typical 2-wire bus configuration a device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. the device that controls the message is called a master. the devices that are controlled by the master are referred to as slaves. the master device generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. the cw24cxx operates as a slave on the i2c-bus. data transfer may be initiated only when the bus is not busy (both data and clock lines remain high). each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop condi- tions is not limited, and is determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition(s). a low-to- high transition of the data line while the clock is high is defined as the stop condition (p), see figure 5. figure 5. definition of start and stop condition v cc peripheral cw24cxx mpu sda scl r p r p 2-wire serial data bus sda scl s start condition stop condition p sda scl
8 rev 1.1 CW24C02/ cw24c04/ cw24c08/ cw24c16 september. 2007 detailed operating information(continued) bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal, as shown in figure 6. figure 6. bit transfer acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit (see figure 7). figure 7. acknowledge on the i2c bus the device that acknowledges must pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). a master receiver must signal an end of data to the transmitter by not generating an acknowledge- ment on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. data output by transmitter data output by receiver scl from master start condition s 12 89 not acknowledge acknowledge clock pulse for acknowledgement data line stable; data valid change of data allowed sda scl
9 rev 1.1 CW24C02/ cw24c04/ cw24c08/ cw24c16 september. 2007 detailed operating information(continued) device addressing the eeprom devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see to figure 8). the device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. this is common to all the serial eeprom devices. the next 3 bits are the a2, a1 and a0 device address bits for the CW24C02. these 3 bits must compare to their corresponding hardwired input pins. the cw24c04 only uses the a2 and a1 device address bits with the third bit being a memory page address bit. two device address bits must compare to their corresponding hardwired input pins. the a0 pin is no connected. the cw24c08 only uses the a2 device address bit with the next 2 bits being for memory page addressing. the a2 bit must compare to its corresponding hard-wired input pin. the a1 and a0 pins are no connected. the cw24c16 does not use any device address bits but instead the 3 bits are used for memory page addressing. these page addressing bits on the cw24c04/08/16 devices should be considered the most significant bits of the data word address which follows. the a0, a1 and a2 pins are no connected. the eighth bit of the device address is the read/write operation select bit. a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. upon a compare of the device address, the eeprom will output a "0". if a compare is not made, the chip will return to a standby state. figure 8. device address CW24C02 1 0 1 0 a2 a1 a0 r/w msb lsb 1 0 1 0 a2 a1 p0 r/w 1 0 1 0 a2 p1 p0 r/w 1 0 1 0 p2 p1 p0 r/w device operation standby mode the eeprom features a low-power standby mode which is enabled: (1) upon power-up and (2) after the receipt of the stop bit and the completion of any internal operations. cw24c04 cw24c08 cw24c16
10 rev 1.1 CW24C02/ cw24c04/ cw24c08/ cw24c16 september. 2007 memory reset after an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: (1) clock up to 9 cycles. (2) look for sda high in each cycle while scl is high. (3) create a start condition. write operation 1. byte write a write operation requires an 8-bit data word address following the device address word and acknowledgment. upon receipt of this address, the eeprom will again respond with a "0" and then clock in the first 8bit data word. following receipt of the 8-bit data word, the eeprom will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. at this time the eeprom enters an internally timed write cycle, t wr , to the nonvolatile memory. all inputs are disabled during this write cycle and the eeprom will not respond until the write is complete (see figure 9). figure 9. byte write sda line s t a r t m s b device address l s b r / w a c k m s b l s b a c k data a c k s t o p word address w r i t e detailed operating information(continued) 2. page write the CW24C02 device is capable of an 8-byte page write, and the cw24c04/08/16 devices are capable of 16-byte page writes. a page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. instead, after the eeprom acknowledges receipt of the first data word, the microcontroller can transmit up to 7 (CW24C02) or 15 (cw24c04/08/16) more data words. the eeprom will respond with a "0" after each data word received. the microcontroller must terminate the page write sequence with a stop condi- tion (see figure 10). the data word address lower 3 (CW24C02) or 4 (cw24c04/08/16) bits are internally incre- mented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than 8 (CW24C02) or 16 (cw24c04/08/16) data words are transmitted to the eeprom, the data word address will "roll over" and previous data will be overwritten.
11 rev 1.1 CW24C02/ cw24c04/ cw24c08/ cw24c16 september. 2007 figure 10. page write sda line s t a r t m s b device address l s b r / w a c k m s b l s b a c k data( n ) a c k word address(n) a c k data( n+1 ) a c k s t o p data( n+x ) w r i t e detailed operating information(continued) 3. acknowledge polling once the internally timed write cycle has started and the eeprom inputs are disabled, acknowl- edge polling can be initiated. this involves sending a start condition followed by the device address word. the read/write bit is representative of the operation desired. only if the internal write cycle has completed will the eeprom respond with a "0", allowing the read or write sequence to continue. see figure 11 for flow diagram read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to "1". there are three read operations: current address read, random address read and sequential read. send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0)? next operation no yes figure 11. acknowdge polling flow
12 rev 1.1 CW24C02/ cw24c04/ cw24c08/ cw24c16 september. 2007 1. current address read the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. the address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. the address "roll over" during write is from the last byte of the current page to the first byte of the same page. once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the eeprom, the current address data word is serially clocked out. the microcontroller does not respond with an input "0" but does generate a following stop condition (see figure 12). figure 12. current address read sda line s t a r t m s b device address l s b r / w a c k n o a c k s t o p r e a d data detailed operating information(continued) 2. random read a random read requires a "dummy" byte write sequence to load in the data word address. once the device address word and data word address are clocked in and acknowledged by the eeprom, the microcontroller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. the eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a "0" but does generate a following stop condition (see figure 12). figure 13. random read sda line s t a r t m s b device address l s b r / w a c k m s b l s b a c k word address(n) w r i t e s t a r t m s b device address l s b r / w a c k n o a c k s t o p r e a d data( n ) dummy write
13 rev 1.1 CW24C02/ cw24c04/ cw24c08/ cw24c16 september. 2007 3. sequential read sequential reads are initiated by either a current address read or a random address read. after the microcontroller receives a data word, it responds with an acknowledgement. as long as the eeprom receives an acknowledgement, it will continue to increment the data word address and serially clock out sequential data words. when the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. the sequential read operation is terminated when the microcontroller does not respond with a "0" but does generate a following stop condition (see figure 13). figure 14. sequential read device address r / w a c k data( n ) a c k a c k data( n+1 ) data( n+2 ) r e a d sda line a c k n o a c k s t o p data( n+x ) detailed operating information(continued) typical application figure 15. cascades of two eeprom vcc scl sda vcc gnd 4 a0 1 a1 2 vcc 8 sda 5 wp 7 scl 6 a2 3 u1 CW24C02 gnd 4 a0 1 a1 2 vcc 8 sda 5 wp 7 scl 6 a2 3 u2 CW24C02 r1 10k r2 10k device address ? 0xa2 device address ? 0xa0
14 rev 1.1 CW24C02/ cw24c04/ cw24c08/ cw24c16 september. 2007 physical dimensions a a1 a2 a3 b b1 c c1 c2 4.95 5.15 0.37 0.47 1.27(typ) 0.41(typ) 5.80 6.20 3.80 4.00 0.55 0.65 c4 d d1 r1 r2 0.05 0.20 1.05(typ) 0.20(typ) 0.07(typ) 13 (typ) 4 (typ) 12 (typ) 1 2 3 4 b2 0.65 0.55 1.30 1.50 5.0(typ) c3 17 (typ) a2 a3 a a1 b2 c 4 d1 r2 r1 1 c 2 c c 3 c d 1 2 3 4 0.40 0.60 0.07(typ) b sop8l physical dimensions symbol dimension(mm) min max symbol dimension(mm) max min 1 b
15 rev 1.1 CW24C02/ cw24c04/ cw24c08/ cw24c16 september. 2007 1 c 2 c 3 c 4 c a1 a2 a3 a4 a5 d2 d1 a b c d dip8l symbol min max a a1 a2 a3 a4 a5 b c 1.524(typ) 0.39 0.53 2.54(typ) 0.66(typ) 0.99(typ) 6.3 6.5 symbol min max c2 c4 d d1 d2 8.20 0.20 7.62 5 (typ) 8.80 0.35 7.87 dimension(mm) dimension(mm) 1 9.30 9.50 c1 7.20 (typ) 3.30 3.50 2 3 c3 0.5 (typ) 3.3 (typ) 8 (typ) 8 (typ) 1.57(typ) 3 2 1
16 rev 1.1 CW24C02/ cw24c04/ cw24c08/ cw24c16 september. 2007 symbol min max symbol min max dimension(mm) dimension(mm) tssop 8 d 2.90 3.10 e e1 4.30 4.50 a 1.20 a2 0.80 1.05 b 0.19 0.30 f l 0.45 0.75 l1 1.00(typ) e1 pin 1 indicator this co r ner e l l1 a1 a d b f 0.65(typ) 6.40(typ)
17 rev 1.1 CW24C02/ cw24c04/ cw24c08/ cw24c16 september. 2007 dfn8 symbol symbol min max min max dimension(mm) dimension(mm) b2 c5 3.05 2.95 1.95 2.05 a a1 a a1 b b1 b2 0.05 0.20 c c1 c2 c3 c4 c5 1.55 1.65 0.30 0.20 0.50 1.65 1.75 0.35 0.45 1.50 b b1 c c1 c2 c3 c4 0.90 0.80 pin #1 identfication chamfer 0.30 x 45 pin 1# dot by marking 8l t/slp (2x3mm)

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